Dr. Atif Raza Jafri
Last updated on June 11th, 2020
PERSONAL INFORMATION
Name Dr. Atif Raza Jafri
Email dean.es@bahria.edu.pk
atifraza.buic@bahria.edu.pk
Phone 051-92-51-9260002
Research Area Embedded Systems

Computer Architecture and ASIP Implementation at High Abstraction Level

Digital Design

Turbo Processes in Digital Communications

Software Defined Radio (SDR)

Reconfigurable Architecture

FPGA Implementations

Number of Publications 23
AFFILIATIONS
Designation Dean (Engineering Sciences) & Professor
Department Department of Electrical Engineering
University Bahria University Islamabad Campus
QUALIFICATION
DEGREE PASSING YEAR MAJORS UNIVERSITY
PhD (Electrical Engineering) 2011 Multi-ASIP Architecture for Flexible Turbo Receiver Télécom Bretagne, Brest France
MS (Embedded Systems) 2007 Embedded Systems University of Nice Sophia Antipolis, Nice France.
BSc. Electrical Engineering 1999 Embedded Systems University of Engineering & Technology Lahore
TEACHING EXPERIENCE
DESIGNATION FROM TO ORGANIZATION
Professor July 2018 Present Bahria University, Islamabad
Senior Associate Professor Dec 2015 June 2018 Bahria University, Islamabad
Visiting Faculty Member Sept 2013 Dec 2015 Bahria University, Islamabad
INDUSTRIAL EXPERIENCE
DESIGNATION FROM TO ORGANIZATION
System Engineer Feb 2011 Dec 2015 Advanced Engineering and Research Organisation
Digital Designer Nov 1999 Sept 2006 Advanced Engineering Research Organization, Hassan Abdal, Pakistan
EUROPEAN PROJECTS
Worked in Project AFANA, NEWCOM++ and UDEC funded by French National Research Agency

·         EquASIP Design, Modelling and FPGA Validation:

An ASIP for multi-Wireless Standard MIMO Decoding Applications implementing MMSE Equalization.

·         DemASIP Design, Modelling and FPGA Validation:

An ASIP for multi-Wireless Standard Demodulation Applications implementing ML Demapping.

·         TurbASIP Enhancement, Modelling and FPGA Validation:

An ASIP for multi-Wireless Standard Turbo Decoding Applications implementing Max-Log MAP Decoding.

·         Baseband Transmitter, Channel Emulator and Receiver:

Multiple FPGA Prototypes implementing a transmission system made up of Transmitter, Channel Emulator and Turbo Receiver. On transmitter flexible components such as Turbo Encoder, BICM interleaver, flexible modulator (flexible for BPSK to 256-QAM), SSD Element and MIMO unit for Space Time Coder were written in VHDL and finally implemented on FPGA. AWGN and Rayleigh Fading Channel Emulator for single antenna and MIMO applications were built to add channel effects in transmitted data. On the receiver side multiple instances of EquASIP, DemASIP and TurbASIP (9 ASIPs in total) and 3 Network on Chip (NoC) were integrated to achieve turbo decoding, turbo demodulation and MIMO turbo equalization principles to achieve error rate performance close to theoretical limits.

·         Communication System software Modelling:

C/C++ Software Models simulating digital communication systems were created to analyze parallelism in turbo demodulation and turbo equalization in the context of execution time gain versus area overhead.

Proposal for the parameterized demapper for Reconfigurable MODEM. System C and VHDL modeling of the proposed Configurable Demapper Architecture for French project IDROMEL.

FUNDED PROJECTS
  • One of the Co-PIs in National Centre in Cyber Security for FPGA Prototyping of Intrusion Detection System.
FOREIGN COLLABORATION 
IMT Atlantique, France

  • IMT Atlantique invited and funded a visit in January, 2018 to develop
    1. FPGA based “Correlated Fading Channel Emulator through Overlap-Save Method” as part of 5G Test Bed.
    2. Turbo receiver for high data rate
    3. 2 ISI impact factor journals publihsed

University of Glasgow, Scotland, UK

  • Working jointly with University of Glasgow (Wireless Communications and RADAR systems” Group at University of Glasgow, Scotland
    1. 5G Waveform implementation on FPGA
    2. One ISI indexed Impact Factor journal published one accepted

Umm-ul- Qura University, Makkah, KSA

  • Project MODEVES (http://modeves.com/deliverables.html)
    1. Created the simulation environment (using QuestaSim tool from Mentor Graphics) where assertion based verification can be accomplished on auto generated SystemVerilog Code.
    2. Created the synthesis environment where auto generated SystemVerilog Code can be synthesized.
    3. Developed a 3 Credit Hour course “From Verilog to Assertion based verification using SystemVerilog”
    4. Developed 1 credit hour lab for above stated course.
  • Asymmetric Crypto Processor Implementations
    1. Jointly worked with a research assistant in developing C and Verilog models for point multiplication implementation for Elliptic Curves and Binary Huff Curves (BHC).
    2. 2 Research articles published and 1 accepted in ISI indexed impact factor journal.
    3. Work on ASIP modelling of Asymmetric Cryptography targeting different key lengths and different algorithms is under process
PUBLICATIONS
Book Chapter

  1. A.R. Jafri, A. Baghdadi, and M. Jezequel, “ASIP Design and Prototyping for Wireless Communication Applications”, In “Advanced Applications Of Rapid Prototyping Technology In Modern Engineering” book, InTech Open Access Publisher, 2011, ISBN ISBN 978-953-307-698-0.

Journals

  1. R. Jafri, A. Baghdadi, and M. Jezequel, “Parallel MIMO Turbo Equalization”, IEEE Communication Letters, VOL. 15, NO. 3, MARCH 2011. (Impact Factor = 2.723)
  2. R. Jafri, A. Baghdadi, M. Najam-ul-Islam and M. Jezequel, “Heterogeneous Multi-ASIP and NoC Based Architecture for Adaptive Parallel TBICM-ID-SSD”, IEEE Transaction on Circuit and System II Issue: 3, Vol. 64 DOI 10.1109/TCSII.2016.2555018.(Impact Factor = 2.45)
  3. R. Jafri, A. Baghdadi, M. Waqas and M. Najam-ul-Islam “High-Throughput and Area-Ef?cient Rotated and Cyclic Q Delayed Constellations Demapper for Future Wireless Standards”, IEEE ACCESS, Issue 2017, Volume 5. (Impact Factor = 3.557)
  4. R. Jafri, Javaria Majid, Muhammad Ali Shami, Muhammad Ali Imran and M. Najam-ul-Islam, “Hardware Complexity Reduction in Universal Filtered Multicarrier Transmitter Implementation”, IEEE ACCESS, Issue 2017, Volume 5. (Impact Factor = 3.557)
  5. Malik Imran, Muhammad Rashid, R. Jafri, and M. Najam-ul-Islam “ACryp-Proc: Flexible Asymmetric Crypto Processor for Point Multiplication”, IEEE ACCESS, Issue: Early Access, Pages 1-1, 17, April, 2018. 10.1109/ACCESS.2018.2828319. (Impact Factor = 3.557)
  6. Atif Raza Jafri, Javaria Majid, Lei Zhang, Muhammad Ali Imran, M. Najam-ul-IslamFPGA Implementation of UFMC based Baseband Transmitter: Case Study for LTE 10MHz Channelization” Issue 2018, Pages 1-12 in Wireless Communications and Mobile Computing (Wiley and Hindawi) (Impact Factor = 0.869)
  7. Umar Mujahid, Muhammad Najam-ul-islam, Atif Raza Jafri, Qurat Ul Ain and Muhammad Ali Shami “A New Ultralightweight RFID Mutual Authentication Protocol: SASI using Recursive Hash”, International Journal of Distributed Sensor Networks, 2016, Article ID 9648971, 14 pages, Feb 2016. doi:10.1155/2016/9648971. (Impact Factor = 1.787)
  8. Umar Mujahid, A.R. Jafri, and M. Najam-ul-Islam, “Efficient Hardware Implementation of Ultralightweight RFID Mutual Authentication Protocol”, Journal of Circuits, Systems, and Computers, Vol. 25, No. 7, 19 Pages, March 2016. doi:10.1142/S0218121661650078X. (Impact Factor = 0.595)
  9. R. Jafri, Malik Imran, Muhammad Rashid, and M. Najam-ul-Islam “Towards an Optimized Architecture for Unified Binary Huff Curves” Journal of Circuits, Systems, and Computers, Vol. 26, Issue 11, Pages 1750178-1 to 1750178-14, April, 2017.doi:10.1142/S021812661750178X. (Impact Factor = 0.595)
  10. Malik Imran, Muhammad Rashid and R. Jafri “Flexible Architectures for Cryptographic Algorithms–A  Systematic Literature Review”, accepted in Journal of Circuits, Systems, and Computers. (Impact Factor = 0.595)
  11. R. Jafri, A. Baghdadi, and M. Jezequel, “ASIP-based Universal Demapper for Multiwireless Standards”,      The inauguration issue of IEEE Embedded Systems Letters, vol. 1, no. 1, pp. 9-13, May 2009. (ISI Indexed)

European Project Reports

  1. A.R. Jafri, A. Baghdadi, and others, “Performance evaluation and guidelines for future flexible radio architectures”, Deliverable of NEWCOM++ European project.
  2. R. Hdiji, A. Jafri, K. Khalfallah, R. Knopp, J. Martin, N. Muhammad and R. Pacalet and R. Rasheed and C. Schmidt “IDROMel liverable 1.3.1, version 1.0 Baseband functional specification Preliminary architecture”.

Conferences

  1. A.R. Jafri, D. Karakolah, A. Baghdadi, and M. Jezequel, “ASIP-based Flexible MMSE-IC Linear Equalizer for MIMO Turbo-Equalization Applications”, In Proc. IEEE/ACM Design, Automation and Test in Europe Conference & Exhibition, DATE’09, Nice, France, 21-23 April 2009.
  2. H.Moussa, O. Muller, A.R. Jafri,A. Baghdadi, J. Le Mestre, and M. Jezequel, “FPGA Prototypes For Turbo Communication Applications”, Poster and Demonstration at the University Booth of the IEEE/ACM Design, Automation and Test in Europe Conference & Exhibition, DATE’09, Nice, France, 21-23 April 2009.
  3. A.R. Jafri, A. Baghdadi, and M. Jezequel, “Rapid Prototyping of ASIP-based flexible MMSE-IC Linear Equalizer”, In Proc. IEEE/IFIP 20th International Symposium on Rapid System Prototyping, RSP’09, Paris, France, 23-26 June 2009.
  4. A.R. Jafri, A. Baghdadi, and M. Jezequel, “Rapid Design and Prototyping of Universal Soft Demapper”, In Proc. IEEE International Symposium on Circuits and Systems, ISCAS’10, Paris, France, 30 May – 2 June 2010.
  5. A.R. Jafri, A. Baghdadi, and M. Jezequel, “DemASIP : Universal Demapper for Multiwireless Standards”, In GDR SoC-SiP: Groupe de recherche System on Chip – System in Package, Colloque National, Paris, France, 9-11 June 2010.
  6. A.R. Jafri, A. Baghdadi, and M. Jezequel, “Exploring Parallel Processing Levels in Turbo Demodulation”, In Proc. IEEE 6th International Symposium on Turbo Codes and Iterative Information Processing, Brest, France, 6-10 Sept 2010.
  7. A.R. Jafri, A. Baghdadi, and M. Jezequel, “FPGA Prototypes of Heterogeneous multi-ASIP and NoC based Unified Turbo Receiver for Multi Wireless Standards”, Poster and Demonstration at the University Booth of the IEEE/ACM Design, Automation and Test in Europe Conference & Exhibition, DATE’11, Grenoble, France, 14-18 March 2011.
  8. A.R. Jafri, and A. Baghdadi, “Conversion Throughput Gain in Parallel Turbo Receiver”, In Proc. IEEE  IBCAST’13  , Islamabad ,Pakistan, 15-19 Jan 2013.
  9. Yusra Mehmood, Umar Mujahid, M. Najam-ul-islam, A.R. Jafri,” Efficient Hardware Implementation of lightweight Pseudo-random number generators”, The Second International Conference on Computer Science, Computer Engineering, and Education Technologies (CSCEET2015), Kuala Lumpur, Malaysia, September 8-10, 2015.
  10. Muhammad Rashid, Malik Imran and Atif Raza Jafri, “Comparative Analysis of Flexible Cryptographic Implementations ,11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016), Tallinn – Estonia, June 27-29, 2016.
  11. Malik Imran, Atif Raza Jafri, Imran Shafi and Muhammad Rashid, “Hardware Design and Implementation of ECC based Crypto Processor for Low-area- applications on FPGA” In proc. 11th IEEE International Conference On Open Source Systems And Technologies (ICOSST 2017), 18-20 December, Lahore, Pakistan.
  12. M. Waqas, A.R. Jafri, A. Baghdadi, and M. Najam-ul-Islam “Rapid Prototyping of Parameterized Rotated and Cyclic Q Delayed Constellations Demapper”, In Proc. IEEE/IFIP 29th International Symposium on Rapid System Prototyping, RSP’18, October 4-5, 2018, Torino, Italy.