Engr. Dr. Khalid Javed
Category: Faculty
Published on: January 1, 2015
Last updated on March 7th, 2019

Engr. Dr. Khalid Javed

Head of Department

Senior Assistant Professor

Computer Engineering Department
 
Email  hodceisb@bahria.edu.pk
Phone 051-926002 ext 315
Education PhD in Electrical Engineering (Dublin City University)
Experience 9 years teaching and 1 year industry
Specialization

Computer Architecture

Finite Field Arithmetic

Digital Systems

Signal Processing

Cryptographic Primitives

   
Engr. Dr. Khalid Javed completed his Ph.D. from School of Electronic Engineering, Dublin City University, Dublin, Ireland in 2016. He has done MSc in Electrical Engineering from Linkoping University, Sweden, in 2010 and BS Computer Engineering from COMSATS. He is working as a Senior Assistant Professor and heading Department of Computer Engineering, Bahria University, Islamabad. His research interests include computer architecture, finite field arithmetic digital systems and VLSI architectures for signal processing and cryptographic primitives. He has more than seven years of teaching experience at undergraduate and graduate levels.
  • Hardware accelerators for Finite Field Arithmetic
  • Hardware realization of cryptographic algorithms
  • VLSI architectures
  • Computer architecture

Bahria University, Islamabad , Senior Assistant Professor

August 2017-Present

  COMSATS Abbottabad, Electrical Engineering Department, Lecturer
 June 2007-Sep 2008, Sep 2010 to March 2012 and June 2016 to June 2017

Teaching Digital System Design, Computer Architecture, VLSI, Embedded System Design courses at Undergraduate and Graduate levels

 

Publications

Journal Publications

  1. Khalid Javeed and Xiaojun Wang “Low latency flexible FPGA Implementation of Point Multiplication on Elliptic Curves over GF(p)”, International Journal of Circuit Theory and Applications, 2017 (IF 1.57).
  2. Khalid Javeed, Xiaojun Wang and Mike Scott “High Performance Hardware Support for Elliptic curve Cryptography over general Prime Field”, in Elsevier Microprocessor and Microsystems, Embedded Hardware Design, 2016 (IF 1.025).
  3. Khalid Javeed and Xiaojun Wang “FPGA Based High Speed SPA Resistant Elliptic Curve Scalar Multiplier Architecture”, International Journal of Reconfigurable Computing, Volume 2016 (2016), Article ID 6371403, 10 pages.

 

In Peer Review Publications:

  1. Khalid Javeed and Xiaojun Wang “High-Speed Reconfigurable Parallel Multipliers for ECC Applications”; IET Computers & Digital Techniques.
  2. Yasir Ali Shah, Khalid Javeed and Xiaojun Wang”High-Speed RSD Based Flexible ECC Processor for Arbitrary Curves over General Prime Field" International Journal of Circuit Theory Applications.
  3. Saifullah Khan, Yasir Ali Shah and Khalid Javeed “;High-Speed FPGA Implementation of Full Word Montgomery Multiplier for ECC Applications" Elsevier Microprocessor and Microsystems, Embedded Hardware Design.
  4. Yasir Ali Shah and Khalid Javeed “LUT Based High-Speed ECC Architecture for Standard Primes”; IET Computer and Digital Techniques.

Conference Publications:

  1. Khalid Javeed and Xiaojun Wang “Design and performance analysis of Modular Multipliers on FPGA Platform.”; International Conference on Cloud Computing and Security (ICCCS 2016), Nanjing, China.
  2. Khalid Javeed, Xiaojun Wang “Speed and Area Optimized Higher Radix Modular Multipliers”;Cryptology ePrint Archive, Report 2016/053, 2016.
  3. Khalid Javeed, Xiaojun Wang, and Mike Scott “Serial and Parallel Modular Multipliers over FPGA Platform”; in IEEE international Conference on Field Programmable Logic and Applications (FPL 2015), London, United Kingdom.
  4. Khalid Javeed and Xiaojun Wang “Radix-4 and radix-8 Booth encoded interleaved modular multipliers over general prime field”; in IEEE international Conference on Field Programmable Logic and Applications (FPL 2014), Munich, Germany.
  5. Khalid Javeed and Xiaojun Wang “Efficient Montgomery Multiplier for ECC and Pairing based Cryptography “; in IEEE International Symposium on Communication Systems, Networks Digital Signal Processing (CSNDSP 2014), Manchester, United Kingdom.